Transistor devices having source/drain structure configured with high germanium content portion

ABSTRACT

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a divisional of U.S. application Ser. No. 17/025,077filed Sep. 18, 2020, which in turn claims the benefit of continuationU.S. patent application Ser. No. 16/037,728, filed Jul. 17, 2018, nowU.S. Pat. No. 10,811,496, Issued Oct. 20, 2020, which is a continuationof U.S. application Ser. No. 15/255,902, filed Sep. 2, 2016, now U.S.Pat. No. 10,903,83, Issued Oct. 2, 2018, which is a continuation of U.S.patent application Ser. No. 13/990,249, filed May 29, 2013, now U.S.Pat. No. 9,437,691, Issued Sep. 6, 2016, which claims benefit of PCTInternational Application No. PCT/US2011/066129, filed Dec. 20, 2011,which claims benefit of continuation-in-part U.S. patent applicationSer. No. 12/975,278, filed Dec. 21, 2010, now U.S. Pat. No. 8,901,537,Issued Dec. 2, 2014, the entire disclosures of which are herebyincorporated by reference in their entirety and for all purposes.

BACKGROUND

Increased performance of circuit devices including transistors, diodes,resistors, capacitors, and other passive and active electronic devicesformed on a semiconductor substrate is typically a major factorconsidered during design, manufacture, and operation of those devices.For example, during design and manufacture or forming of metal oxidesemiconductor (MOS) transistor semiconductor devices, such as those usedin a complementary metal oxide semiconductor (CMOS), it is often desiredto minimize the parasitic resistance associated with contacts otherwiseknown as external resistance Rext. Decreased Rext enables higher currentfrom an equal transistor design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates components of resistance of a typicalMOS transistor that includes source and drain tip regions.

FIG. 2 is a method of forming a column IV transistor in accordance withan embodiment of the present invention.

FIGS. 3A to 3F illustrate structures that are formed when carrying outthe method of FIG. 2, in accordance with various embodiments of thepresent invention.

FIGS. 4A to 4G each shows a perspective view of a FinFET transistorstructure formed in accordance with one embodiment of the presentinvention.

FIGS. 5A and 5B each shows a perspective view of a nanowire transistorstructure formed in accordance with an embodiment of the presentinvention.

FIG. 6 illustrates a computing system implemented with one or moretransistor structures in accordance with an example embodiment of thepresent invention.

As will be appreciated, the figures are not necessarily drawn to scaleor intended to limit the claimed invention to the specificconfigurations shown. For instance, while some figures generallyindicate straight lines, right angles, and smooth surfaces, an actualimplementation of a transistor structure may have less than perfectstraight lines and/or right angles, and some features may have surfacetopology or otherwise be non-smooth, given real world limitations of theprocessing equipment and techniques used. In short, the figures areprovided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for forming column IV transistor devices havingsource and drain regions with high concentrations of germanium, andexhibiting reduced parasitic resistance relative to conventionaldevices. In some example embodiments, the source/drain regions of theresulting transistor structure each include a thin p-type silicon orgermanium or silicon germanium (SiGe) liner layer with the remainder ofthe source/drain material being p-type germanium or a germanium alloycomprising, for instance, germanium and tin, and having a germaniumcontent of at least 80 atomic % (and 20 atomic % or less othercomponents, such as tin and/or other suitable strain inducers). In someexample cases, evidence of strain relaxation may be observed in thisgermanium rich layer including misfit dislocations and/or threadingdislocations. Numerous transistor configurations and suitablefabrication processes will be apparent in light of this disclosure,including both planar and non-planar transistor structures (e.g.,FinFETs and nanowire transistors), as well as strained and unstrainedchannel structures. The techniques are particularly well-suited forimplementing p-type MOS (PMOS) devices, although other transistorconfigurations may benefit as well.

General Overview

As previously explained, increased drive current in the transistors cangenerally be achieved by reducing device external resistance, Rext.However, PMOS transistor performance is a function of various componentresistances within the device, as can be seen with reference to FIG. 1.Channel resistance R1 can be modulated through carrier mobility, whichis a function of compressive strain within the channel. Externalresistance Rext of the device includes tip resistance R2 (tip region isalso referred to as source/drain extension), source/drain resistance R3,and contact resistance R4 (metal to semiconductor). All of thesesegmented resistances have a material component (e.g., energy barrieracross an interface, carrier concentration and mobility) a geometrycomponent (e.g., length, width, etc) and a dynamic electrical loadcomponent (current crowding).

Thus, and in accordance with some embodiments of the present invention,replacing the typical silicon or SiGe alloy materials in thesource/drain regions with a p-type thin liner and high content ofgermanium (with very high p-type doping concentration) minimizes theexternal resistance components (R2, R3, and R4). In addition, byintroducing a highly compressively strained material, the channel holemobility is maximized or otherwise increased and hence reduces channelresistance (R1). The net impact of decreased channel, tip, source/drainand contact resistance is improved transistor current for a givenvoltage (relative to threshold voltage, Vt, i.e. V-Vt).

In some example cases, the thin liner is p-type doped silicon orgermanium or SiGe alloy, and is generally less than 50% of the totalsource/drain deposition layer thickness. The remaining source/draindeposition layer thickness is generally greater than 50% of the totalsource/drain deposition layer thickness and can be, for example, p-typedoped germanium or a germanium alloy such as germanium:tin orgermanium:tin:x (where x is, for example, silicon or other marginalcomponent or process/diffusion-based artifact) having at least 80 atomic% germanium and 20 atomic % or less of other constituents (e.g., tinand/or any other suitable strain inducer and/or other marginalunintentional components). In some specific such example embodiments,the thickness ratio of the source/drain liner to the high concentrationgermanium cap is about 1:5 or less (where the liner makes up about 20%or less of the total source/drain deposition layer thickness). In somesuch example cases, the thickness liner is one to several monolayers.

The techniques can be used to form transistor devices in any number ofdevices and systems. In some embodiments, such as CMOS devices havingboth n-type MOS (NMOS) and PMOS transistors, selectivity can be achievedin various ways. In one embodiment, for instance, deposition on NMOSsource/drain locations can be avoided by having NMOS regions masked offduring PMOS deposition. In other embodiments, selectivity may includenatural selectivity. For instance, while boron doped germanium grows onp-type SiGe (or silicon) source drain regions, it does not grow oninsulator surfaces such as silicon dioxide (SiO2) or silicon nitride(SiN); nor does it grow on, for instance, exposed heavily phosphorousdoped silicon in n-type regions.

The techniques provided herein can be employed to improve deviceresistance in any number of transistor structures and configurations,including planar, flush or raised source/drain, non-planer (e.g.,nanowire transistors and finned transistors such as double-gate andtrigate transistor structures), as well as strained and unstrainedchannel structures. The source/drain areas can be recessed (e.g., usingan etch process) or not recessed (e.g., formed on top surface ofsubstrate). In addition, the transistor devices may optionally includesource and drain tip regions that are designed, for instance, todecrease the overall resistance of the transistor while improving shortchannel effects (SCE), but such tip regions are not required. Thetransistor devices may further include any number of gateconfigurations, such as poly gates, high-k dielectric metal gates,replacement metal gate (RMG) process gates, or any other gate structure.Any number of structural features can be used in conjunction with lowresistance transistor techniques as described herein.

A transmission electron microscopy (TEM) cross-section perpendicular togate lines or secondary ion mass spectrometry (SIMS) profile can be usedto show the germanium concentration in the structure, as profiles ofepitaxial alloys of silicon and SiGe can readily be distinguished fromhigh germanium concentration profiles, in accordance with someembodiments. In some such silicon-containing substrate cases, byforgoing the typical requirement to maintain strained (dislocation free)source/drain regions, the lattice dimension mismatch between thesource/drain fill material and silicon channel can be increased by atleast 2×for pure germanium and even more for germanium-tin alloys. Whilenot 100% of the strain is able to transfer to the channel in cases wheredislocations are present in the germanium rich cap layer, postdeposition thermal treatments can be used to provide a clear transistorperformance (current at a given V-V_(t)) gain even for relaxed films (asdescribed herein) relative to strained SiGe controls. As will beappreciated, relaxed generally means that the films can have misfitdislocations present, but may also refer to a plastic relaxationmechanism which involves dislocation formation and propagation. Aprocess of elastic relaxation becomes possible in non-planarconfigurations such as FinFET (e.g., tri-gate) and nanowire structureswhere the strained material is not fully constrained by the substrate.Thus, the in-plane lattice constant has more flexibility to expand orcontract independent of the substrate and this process does not requireformation and propagation of misfit dislocations. Going forward herein,the word relaxation is used in the sense of plastic relaxation and notin the sense of elastic relaxation. The use of tin or other suitablestrain inducers to alloy the high concentration germanium cap asdescribed herein can optionally be used to increase the strain in thechannel region, and thereby further reduce the overall device resistancevia reduction in resistance R1 in FIG. 1. As will further beappreciated, while defect free pure germanium may be desirable, it isgenerally difficult to grow defect free for deposition on, for example,a silicon substrate or even SiGe substrate having say 50 atomic %germanium. Surprisingly, however, if performance of a typical fullystrained SiGe layer and such a germanium-rich layer having some defects(e.g., has misfit and/or threading dislocations) were compared, then thedefective germanium-rich layer would perform better. As will beappreciated, this result is generally not intuitive, as it runs counterto the conventional understanding with respect to thin film. In anycase, while some embodiments of the present invention may includegermanium-rich caps that are lacking in crystal features such as misfitdislocations, threading dislocations and twins (defects resulting from achange in lattice orientation across a twin plane), other embodimentsmay include germanium-rich caps that have one or more such features.

Architecture and Methodology

FIG. 2 is a method of forming a column IV transistor in accordance withan embodiment of the present invention. FIGS. 3A to 3F illustrateexample structures that are formed when carrying out the method of FIG.2, in accordance with various embodiments. One or more such transistorsmay be formed in the fabrication of, for example, a processor or acommunications chip or memory chip. Such integrated circuits can then beused in various electronic devices and systems.

The example method includes forming 202 one or more gate stacks on asemiconductor substrate upon which a MOS device may be formed. The MOSdevice may comprise, for example, PMOS transistors, or both NMOS andPMOS transistors (e.g., for CMOS devices). FIG. 3A shows an exampleresulting structure, which in this case includes a PMOS transistorformed on substrate 300. As can be seen, the gate stack is formed over achannel region, and includes a gate dielectric layer 302, a gateelectrode 304, and an optional hardmask 306. Spacers 310 are formedadjacent to the gate stack.

The gate dielectric 302 can be, for example, any suitable oxide such assilicon dioxide (SiO2) or high-k gate dielectric materials. Examples ofhigh-k gate dielectric materials include, for instance, hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. In some embodiments, an annealing processmay be carried out on the gate dielectric layer 302 to improve itsquality when a high-k material is used. In some specific exampleembodiments, the high-k gate dielectric layer 302 may have a thicknessin the range of 5 A to around 100 A thick (e.g., 10 A). In otherembodiments, the gate dielectric layer 302 may have a thickness of onemonolayer of oxide material. In general, the thickness of the gatedielectric 302 should be sufficient to electrically isolate the gateelectrode 304 from the source and drain contacts. In some embodiments,additional processing may be performed on the high-k gate dielectriclayer 302, such as an annealing process to improve the quality of thehigh-k material.

The gate electrode 304 material can be, for example, polysilicon,silicon nitride, silicon carbide, or a metal layer (e.g., tungsten,titanium nitride, tantalum, tantalum nitride) although other suitablegate electrode materials can be used as well. The gate electrode 304material, which may be a sacrificial material that is later removed fora replacement metal gate (RMG) process, has a thickness in the range ofabout 10A to 500A (e.g., 100A), in some example embodiments.

The optional gate hard mask layer 306 can be used to provide certainbenefits or uses during processing, such as protecting the gateelectrode 304 from subsequent etch and/or ion implantation processes.The hard mask layer 306 may be formed using typical hard mask materials,such as silicon dioxide, silicon nitride, and/or other conventionalinsulator materials.

The gate stack can be formed as conventionally done or using anysuitable custom techniques (e.g., conventional patterning process toetch away portions of the gate electrode and the gate dielectric layersto form the gate stack, as shown in FIG. 2A). Each of the gatedielectric 302 and gate electrode 304 materials may be formed, forexample, using conventional deposition processes such as chemical vapordeposition (CVD), atomic layer deposition (ALD), spin-on deposition(SOD), or physical vapor deposition (PVD). Alternate depositiontechniques may be used as well, for instance, the gate dielectric 302and gate electrode 304 materials may be thermally grown. As will beappreciated in light of this disclosure, any number of other suitablematerials, geometries, and formation processes can be used to implementan embodiment of the present invention, so as to provide a lowresistance transistor device or structure as described herein.

The spacers 310 may be formed, for example, using conventional materialssuch as silicon oxide, silicon nitride, or other suitable spacermaterials. The width of the spacers 310 may generally be chosen based ondesign requirements for the transistor being formed. In accordance withsome embodiments, however, the width of the spacers 310 is not subjectto design constraints imposed by the formation of the source and draintip regions, given sufficiently high p-doped germanium content (e.g.,boron doped germanium) or SiGe alloy liner in the source/drain tipregions.

Any number of suitable substrates can be used to implement substrate300, including bulk substrates, semiconductors-on-insulator substrates(XOI, where X is a semiconductor material such as silicon, germanium, orgermanium-enriched silicon), and multi-layered structures, includingthose substrates upon which fins or nanowires can be formed prior to asubsequent gate patterning process. In some specific example cases, thesubstrate 300 is a germanium or silicon or SiGe bulk substrate, or agermanium or silicon or SiGe on oxide substrate. Although a few examplesof materials from which the substrate 300 may be formed are describedhere, other suitable materials that may serve as a foundation upon whicha low resistance transistor device may be built falls within the spiritand scope of the claimed invention.

With further reference to FIG. 3A, after the one or more gate stacks areformed, the method continues with some optional processing which in thisexample embodiment includes etching 204 the source/drain regions of thetransistor structure, and masking-off 206 any NMOS source/drain regionsof the structure (if present). As will be appreciated, the source/drainregions need not be recessed or otherwise etched. In such cases, thesource/drain materials can be formed on the substrate 300 without anyetching. While such non-recessed source/drain regions will not impactchannel resistance, a bi-layer source/drain structure having a thinliner and high germanium content cap can still be implemented to providelow contact resistance, in accordance with some embodiments. As willfurther be appreciated, not all embodiments will include n-type regions.In some example cases, for instance, the circuit being fabricated mayinclude only PMOS devices. In such example cases, there would be non-type source/drain regions to mask off. When n-type regions arepresent, any suitable masking technique can be used to protect then-type regions during p-type processing.

In example embodiments where the source/drain regions are etched,source/drain cavities 312/314 result, as best shown in FIG. 3A. Thecavities effectively define the location of the source/drain regions. Ascan be further seen, substrate 300 has been etched not only to providesource/drain cavities 312/314, but also their respective tip areas312A/314A which undercut the gate dielectric 302. The cavities 312/314and their respective tip areas 312A/314A can be formed as conventionallydone using any number of suitable processes. In some example cases, thisincludes ion implantation to highly dope portions of substrate 300adjacent to the gate stack followed by annealing to drive the dopantsfurther into substrate 300 to improve the etch rate of the intendedsource/drain areas. A dry etch process can then be used to etch thedoped regions of substrate 300 to form cavities 312/314 and theirrespective tip areas 312A/314A. After the dry etch process hascompleted, a wet etch may be used, for instance, to clean and furtheretch the cavities 312/314 and their respective tip areas 312A/314A. Suchwet etching, which can be carried out using conventional or custom wetetch chemistries, can be used to remove contaminants such as carbon,fluorine, chlorofluorocarbons, and oxides such as silicon oxide toprovide a clean surface upon which subsequent processes may be carriedout. In addition, and assuming a monocrystalline silicon substrate, thewet etching may also be used to remove a thin portion of substrate 300along the <111> and <001>crystallographic planes to provide a smoothsurface upon which a high quality epitaxial deposition may occur. Insome example cases, the thin portion of substrate 300 that is etchedaway may be, for example, up to 5 nm thick and may also remove residualcontaminants. The wet etching generally causes edges of the cavities312/314 and their respective tip areas 312A/314A to follow the <111> and<001>crystallographic planes.

With further reference to FIG. 2, the method continues with depositing208 a p-type silicon or germanium or SiGe liner 313/315 in the p-typesource/drain regions, and then depositing 210 a p-type germanium orgermanium alloy in the p-type source/drain regions over the liner313/315. Each of these depositions can be carried out, for instance,using selective epitaxial deposition, although any suitable depositionprocess can be used. As can be seen with reference to FIG. 3B, thep-type silicon or germanium or SiGe liners 313/315 are deposited intocavities 312/314 and their respective tip areas 312A/314A. In addition,and as best shown in FIG. 3C, cavities 312/314 and tip areas 312A/314Ahave been further filled to provide a thick capping layer of p-typegermanium or germanium alloy 318/320 over the p-type liners 313/315.Example p-type dopants include, for instance, boron, gallium, or anyother suitable p-type dopant or dopants, as will be appreciated, and theclaimed invention is not intended to be limited to any particular one.

In accordance with some specific example embodiments where the substrate300 is a silicon or SiGe bulk substrate, or a semiconductor-on-insulatorsubstrate (XOI, where X is silicon or SiGe), the source and draincavities 312/314 along with their respective tip areas 312A/314A arefilled with in-situ boron doped silicon or SiGe thereby forming thecorresponding liners 313/315, and then further filled with in-situ borondoped germanium or germanium rich alloy to provide caps 318/320. Inother example embodiments where the substrate 300 is a germanium bulksubstrate or a germanium-on-insulator substrate, the source and draincavities 312/314 along with their respective tip areas 312A/314A can befilled with in-situ boron doped germanium thereby forming thecorresponding liners 313/315, and then further filled with in-situ borondoped germanium rich alloy (such as germanium:tin) to provide caps318/320. As will be appreciated in light of this disclosure, therespective germanium and p-type dopant concentrations of the liners313/315 and caps 318/320 can vary depending on factors such as thecomposition of the substrate 300, the use of grading for latticematching/compatibility, and the overall desired thickness of the totalsource/drain deposition. Numerous material system and p-type dopingconfigurations can be implemented, as will be appreciated in light ofthis disclosure.

For instance, in some example embodiments having a silicon or germaniumor SiGe substrate, the germanium concentration of the liners 313/315 canbe in the range of 20 atomic % to 100 atomic %, and the boronconcentration is in the range of 1E20 cm-3 to 2E21 cm-3. To avoidlattice mismatch with an underlying silicon-containing substrate, thegermanium concentration of the liners 313/315 can be graded, inaccordance with some embodiments. For example, in one such embodiment,the liners 313/315 can be a graded boron doped SiGe layer with thegermanium composition graded from a base level concentration compatiblewith the underlying silicon or SiGe substrate 300 up to 100 atomic % (ornear 100 atomic %, such as in excess of 90 atomic % or 95 atomic % or 98atomic %). In one specific such embodiment, the germanium concentrationranges from 40 atomic % or less to in excess of 98 atomic %. The boronconcentration within liners 313/315 can be fixed, for example, at a highlevel, or alternatively can be graded. For instance, for example, theboron concentration within liners 313/315 can be graded from a baseconcentration at or otherwise compatible with the underlying substrate300 up to a desired high concentration (e.g., in excess of 1E20 cm-3, inexcess of 2E20 cm-3, or in excess of 5E20 cm-3). In some suchembodiments, the boron doped germanium caps 318/320 have a boronconcentration in excess of 1E20 cm-3, such as in excess of 2E20 cm-3 orin excess of 2E21 cm-3, or higher. This boron concentration in the caps318/320 can be graded in a similar fashion as described with referenceto the liners 313/315. In a more general sense, the boron concentrationscan be adjusted as necessary to provide the desired degree ofconductivity, as will be appreciated in light of this disclosure. Thegermanium concentration of the caps 318/320 can be, for instance, fixedat 100 atomic %. Alternatively, germanium concentration of the caps318/320 can be graded from a low to high concentration (e.g., from 20atomic % to 100 atomic %), as will be appreciated in light of thisdisclosure, to account for lattice mismatch between the liners 313/315and the desired peak germanium concentration of the caps 318/320. Instill other embodiments, the caps 318/320 are implemented with agermanium alloy, where the blend can be, for example, up to 80 atomic %germanium and up to 20 atomic % for the alloying material, which in someembodiments is tin. Note that the tin concentration (or other alloyingmaterial) can also be graded, as will be appreciated. In one such case,channel strain is increased with a tin concentration in the range of 3to 8 atomic % in the caps 318/320 (with the balance atomic percentage ofthe caps 318/320 substantially being germanium and any gradientmaterial). In spite of relaxation, lattice constants are stillrelatively large and capable of applying significant strain on theadjacent channel. Other suitable tin concentrations will be apparent, aswill other suitable strain inducers.

Note that with a pure germanium substrate, the liners 313/315 can beimplemented with germanium and need not be graded. In some such cases,the germanium concentration of the liners 313/315 can be fixed (e.g.,100 atomic %) and the caps 318/320 can be implemented with a germaniumalloy (e.g., germanium:tin, or other suitable germanium alloy aspreviously described). As previously explained, the germaniumconcentration (or the tin or other alloying material concentration) inthe caps 318/320 can be graded to effect desired channel strain. In somesuch cases, further note that the germanium liners 313/315 caneffectively be integrated with the germanium alloy caps 318/320 orotherwise be an undetectable component of the source/drain regiondeposition.

With respect to gradings, note that compatibility as used herein doesnot necessitate an overlap in concentration levels (for instance, thegermanium concentration of underlying substrate 300 can be 0 to 20atomic % and initial germanium concentration of the liners 313/315 canbe 30 to 40 atomic %). In addition, as used herein, the term ‘fixed’with respect to a concentration level is intended to indicate arelatively constant concentration level (e.g., the lowest concentrationlevel in the layer is within 10% of the highest concentration levelwithin that layer). In a more general sense, a fixed concentration levelis intended to indicate the lack of an intentionally gradedconcentration level.

The thickness of the liners 313/315 and caps 318/320 can also varydepending on factors such as the composition of the substrate 300, theuse of grading for lattice matching/compatibility, and the overalldesired thickness of the total source/drain deposition. In general, theliners 313/315 may be thicker in cases where they are configured with agraded germanium content to provide compatibility with a substrate 300that has no or an otherwise low germanium content. In other cases wherethe substrate 300 is a germanium substrate or otherwise contains arelatively high concentration of germanium, the liners 313/315 need notbe graded, and may therefore be relatively thinner (e.g., one to severalmonolayers). In yet still other cases where the substrate has no or anotherwise low germanium content, the liners 313/315 can be implementedwith a relatively thin layer of silicon or otherwise low germaniumcontent material, and the germanium content of the caps 318/320 can begraded as needed for compatibility. In any such cases, the liners313/315 generally make up less than 50% of the total source/draindeposition layer thickness, and the remaining source/drain depositionlayer thickness is generally greater than 50% of the total source/draindeposition layer thickness. In accordance with some such exampleembodiments where the liners 313/315 are not graded, the thickness ratioof liners 313/315 to caps 318/320 is about 2:5 or less (i.e., where theliner makes up about 40% or less of the total source/drain depositionlayer thickness). In some specific such embodiments, the thickness ratioof liners 313/315 to caps 318/320 is about 1:5 or less (i.e., where theliner makes up about 20% or less of the total source/drain depositionlayer thickness). In one such specific example case, the thickness ofliners 313/315 is in the range of one-to-several monolayers to about 10nm, and the total source/drain deposition layer thickness is in therange of 50 to 500 nm. Numerous source/drain liner and cap geometriesand material configurations will be apparent in light of thisdisclosure.

As will be appreciated in light of this disclosure, any number of othertransistor features may be implemented with an embodiment of the presentinvention. For instance, the channel may be strained or unstrained, andthe source/drain regions may or may not include tip regions formed inthe area between the corresponding source/drain region and the channelregion. In this sense, whether a transistor structure has strained orunstrained channels, or source/drain tip regions or no source/drain tipregions, is not particularly relevant to various embodiments of thepresent invention, and the claimed invention is not intended to belimited to any particular such structural features. Rather, any numberof transistor structures and types, and particularly those structureshaving p-type or both n-type and p-type source/drain transistor regions,can benefit from employing a bi-layer source/drain configuration havinga liner and high germanium concentration cap as described herein.

A CVD process or other suitable deposition technique may be used fordepositing 208 and 210. For example, depositing 208 and 210 may becarried out in a CVD reactor, an LPCVD reactor, or an ultra high vacuumCVD (UHVCVD). In some example cases, the reactor temperature may fall,for instance, between 600° C. and 800° C. and the reactor pressure mayfall, for instance, between 1 and 760 TOIT. The carrier gas may include,for example, hydrogen or helium at a suitable flow rate, such as between10 and 50 SLM. In some specific embodiments, the deposition may becarried out using a germanium source precursor gas such as GeH4 that isdiluted in H2 (e.g., the GeH4 may be diluted at 1-20%). For instance,the diluted GeH4 may be used at a 1% concentration and at a flow ratethat ranges between 50 and 300 SCCM. For an in situ doping of boron,diluted B2H6 may be used (e.g., the B2H6 may be diluted in H2 at 1-20%).For instance, the diluted B2H6 may be used at a 3% concentration and ata flow rate that ranges between 10 and 100 SCCM. In some example cases,an etching agent may be added to increase the selectivity of thedeposition. For instance, HCl or C12 may be added at a flow rate thatranges, for example, between 50 and 300 SCCM.

Numerous variations on the source/drain bi-layer construction will beapparent in light of this disclosure. For instance, in some embodiments,the liners 313/315 are implemented with epitaxially deposited borondoped SiGe, which may be in one or more layers, and have a germaniumconcentration in the range of 30 to 70 atomic %, or higher. Aspreviously explained, this germanium concentration of the SiGe liner maybe fixed or graded so as to increase from a base level (near substrate300) to a high level (e.g., in excess of 50 atomic %, near a baseconcentration of the germanium concentration of caps 318/320, whichcontinue with the germanium gradient to 100 atomic %). The boronconcentration in some such embodiments can be in excess of 1E20 cm-3,such as higher than 5E20 cm-3 or 2E21 cm-3, and may also be graded so asto increase from a base level near substrate 300 to a high level (e.g.,in excess of 1E20 cm-3 or 2E20 cm-3 or 3E20 cm-3, etc, near caps318/320). In embodiments where the germanium concentration of borondoped SiGe liners 313/315 is fixed, a thin graded buffer may be used tobetter interface the liners 313/315 with the boron doped caps 318/320.Note this buffer can be an intermediate layer or otherwise integratedinto the composition of the caps 318/320. For purposes of thisdisclosure, such a buffer can be treated as part of the caps 318/320.The thickness of the boron doped SiGe deposited layer (or collection oflayers) 313/315 may range, for example, from monolayers to 50 nm, andthe layer (or collection of layers) 318/320 may have a thickness in therange, for example, of 51 to 500 nm, in accordance with some specificembodiments, although alternative embodiments may have other liner andcap thicknesses, as will be apparent in light of this disclosure. Insome embodiments, note that cavities 312/314 may be created underneaththe spacers during cyclical deposition-etch processing, and thosecavities 312/314 can be backfilled by an epitaxial cap layer as well(which can have, for example, the same composition as the boron dopedgermanium caps 318/320).

As will further be appreciated in light of this disclosure, thecombination of high germanium concentration (e.g., in excess of 50atomic % and up to pure germanium) and high boron concentration (e.g.,in excess of 1E20 cm-3), as discussed herein, can be used to realizesignificantly higher conductance in the source and drain regions (R3 inFIG. 1) as well as their respective tip regions (R2 in FIG. 1) in PMOStransistor devices. Further, and as previously explained, since borondiffusion is sufficiently suppressed in high germanium compositionlayers relative to lower germanium composition layers, less adverse SCEdegradation is realized with subsequent thermal anneals when comparingto a lower germanium composition layer with equal p-type dopant speciesand doping levels despite high doping levels in the deposited stressorfilm. Barrier height lowering is also enabled from the higherconcentration of germanium at the contact surface resulting in lowercontact resistance R4 in FIG. 1. In some example embodiments, agermanium concentration in excess of 80 atomic % and up to puregermanium (100 atomic %) can be used to achieve such benefits. Note thatpure germanium is not required, however. For instance, some embodimentsmay have a germanium concentration in excess of 90 or 95 atomic %, butnot be pure.

As further seen with reference to FIG. 3C, forming the source/drain tips318A/320A in relatively close proximity to the channel region alsoimparts a larger hydrostatic stress on the channel. This stressincreases the strain within the channel, thereby increasing mobility inthe channel and increasing drive current. This stress can be furtheramplified by increasing the germanium concentration of the source/draintips 318A/320A in the case of a silicon-containing substrate, and byincreasing the tin concentration in the case of a germanium substrate.This is an improvement over diffusion-based processes where the tipregions generally do not induce a strain on the channel region.

Once the source and drain regions are filled in accordance with anembodiment of the present invention, various conventional MOS processingcan be carried out to complete fabrication of a MOS transistor, such asreplacement gate oxide processes, replacement metal gate processes,annealing, and salicidation processes, that may further modify thetransistor and/or provide the necessary electrical interconnections. Forinstance, after the epitaxial deposition of the source/drain regionsalong with their respective tips, and with further reference to FIG. 2,the method may continue with removing 212 any masking from n-typeregions and processing those regions as desired (if applicable, such asin a CMOS process), and depositing 214 an insulator over the transistor,and then planarizing that insulator layer as commonly done. Theinsulator layer may be formed using materials known for theapplicability in insulator layers for integrated circuit structures,such as low-k dielectric (insulator) materials. Such insulator materialsinclude, for example, oxides such as silicon dioxide (SiO2) and carbondoped oxide (CDO), silicon nitride, organic polymers such asperfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass(FSG), and organosilicates such as silsesquioxane, siloxane, ororganosilicate glass. In some example configurations, the insulatorlayer may include pores or other voids to further reduce its dielectricconstant. FIG. 3D illustrates an example insulator layer 322 that hasbeen deposited and then planarized down to the hard mask 306.

As can be further seen with reference to FIG. 3D′, some embodiments ofthe present invention use a replacement metal gate process, and themethod may include removing the gate stack (including the high-k gatedielectric layer 302, the sacrificial gate electrode 304, and the hardmask layer 306) using an etching process as conventionally done. Inalternate implementations, only the sacrificial gate 304 is removed. Ifthe gate dielectric 302 is removed, the method may include depositing anew gate dielectric layer into the trench opening. Any suitable high-kdielectric materials such as those previously described may be usedhere, such as hafnium oxide. The same deposition processes may also beused. Replacement of the gate dielectric 302 may be used, for example,to address any damage that may have occurred to the original gatedielectric layer during application of the dry and wet etch processes,and/or to replace a low-k or sacrificial dielectric material with ahigh-k or otherwise desired gate dielectric material. The method maythen continue with depositing the metal gate electrode layer into thetrench and over the gate dielectric layer. Conventional metal depositionprocesses may be used to form the metal gate electrode layer, such asCVD, ALD, PVD, electroless plating, or electroplating. The metal gateelectrode layer may include, for example, a p-type workfunction metal,such as ruthenium, palladium, platinum, cobalt, nickel, and conductivemetal oxides, e.g., ruthenium oxide. In some example configurations, twoor more metal gate electrode layers may be deposited. For instance, aworkfunction metal may be deposited followed by a suitable metal gateelectrode fill metal such as aluminum. FIG. 3D′ illustrates an examplehigh-k gate dielectric layer 324 and a metal gate electrode 326 thathave been deposited into the trench opening, in accordance with oneembodiment. Note that such a RMG process may be carried out at adifferent time in the process, if so desired.

With further reference to FIG. 2, after insulator layer 322 is provided(and any desired pre-contact formation RMG process), the methodcontinues with etching 216 to form the source/drain contact trenches.Any suitable dry and/or wet etch processes can be used. FIG. 3E showsthe source/drain contact trenches after etching is complete, inaccordance with one example embodiment.

The method then continues with depositing 218 contact resistancereducing metal and annealing, and then depositing 220 the source/draincontact plugs. FIG. 3F shows the contact resistance reducing metals 325,which in some embodiments include silver, nickel, aluminum, titanium,gold, gold-germanium, nickel-platinum or nickel-aluminum, and/or othersuch resistance reducing metals or alloys. FIG. 3F further shows thecontact plug metal 329, which in some embodiments includes aluminum ortungsten, although any suitably conductive contact metal or alloy can beused, such as silver, nickel-platinum or nickel-aluminum or other alloysof nickel and aluminum, or titanium, using conventional depositionprocesses. Metalization of the source/drain contacts can be carried out,for example, using a germanidation process (generally, deposition ofcontact metal and subsequent annealing). For instance, germanidationwith nickel, aluminum, nickel-platinum or nickel-aluminum or otheralloys of nickel and aluminum, or titanium with or without germaniumpre-amorphization implants can be used to form a low resistancegermanide. The boron doped germanium caps 318/320 allow formetal-germanide formation (e.g., nickel-germanium). The germanide allowsfor significantly lower Schottky-barrier height and improved contactresistance over that in conventional metal-silicide systems. Forinstance, conventional transistors typically use a source/drain SiGe epiprocess, with germanium concentration in the range of 30-40 atomic %.Such conventional systems exhibit Rext values of about 140 Ohm-um,limited by epi/silicide interfacial resistance, which is high and mayimpede future gate pitch scaling. Some embodiments of the presentinvention allow for a significant improvement in Rext in PMOS devices(e.g., a 2× or better improvement, such as an Rext of about 70 Ohm-um,or less), which can better support PMOS device scaling. Thus,transistors having a source/drain configured with a bi-layersource/drain structure as described herein, can exhibit relatively lowerRext values compared to conventional transistors.

Non-Planar Configuration

A non-planar architecture can be implemented, for instance, usingFinFETs or nanowire configurations. A FinFET is a transistor builtaround a thin strip of semiconductor material (generally referred to asthe fin). The transistor includes the standard field effect transistor(FET) nodes, including a gate, a gate dielectric, a source region, and adrain region. The conductive channel of the device resides on/within theouter sides of the fin beneath the gate dielectric. Specifically,current runs along both sidewalls of the fin (sides perpendicular to thesubstrate surface) as well as along the top of the fin (side parallel tothe substrate surface). Because the conductive channel of suchconfigurations essentially resides along the three different outer,planar regions of the fin, such a FinFET design is sometimes referred toas a tri-gate FinFET. Other types of FinFET configurations are alsoavailable, such as so-called double-gate FinFETs, in which theconductive channel principally resides only along the two sidewalls ofthe fin (and not along the top of the fin).

FIGS. 4A to 4G each shows a perspective view of a FinFET transistorstructure formed in accordance with one embodiment of the presentinvention. The previous discussion with respect to FIGS. 2 through 3F isequally applicable here, as will be appreciated. As can be seen, theexample non-planar configuration shown in FIG. 4A is implemented with afin structure which includes a substrate 400 having a semiconductor bodyor fin 410 extending from the substrate 400 through shallow trenchisolation (STI) layer 420. The substrate may be, for example, silicon,germanium, or SiGe.

FIG. 4B shows a gate electrode 440 formed over three surfaces of the fin410 to form three gates (hence, a tri-gate device). A gate dielectricmaterial 430 is provided between the fin 410 and gate electrode 440, andhard mask 450 is formed on top of the gate electrode 440. FIG. 4Cillustrates the resulting structure after deposition of insulatingmaterial and subsequent etch that leaves a coating of the insulatormaterial on all vertical surfaces, so as to provide spacers 460.

FIG. 4D illustrates the resulting structure after an additional etchtreatment to eliminate excess insulating/spacer material from sidewallsof fin 410, thereby leaving only spacers 460 opposite sidewalls of thegate electrode 440. FIG. 4E illustrates the resulting structure after arecess etch to remove fin 410 in the source/drain region of substrate400, thereby forming recess 470. Note that other embodiments may not berecessed (e.g., source/drain region is flush with STI layer 420).

FIG. 4F illustrates the resulting structure after growth of epitaxialliner 480, which may be thin, p-type and contain significant fraction ofsilicon (e.g., silicon or SiGe having 70 atomic % silicon), or be puregermanium (e.g., a separate layer of germanium, or a non-detectablelayer that is integrated or otherwise included in the composition of thecaps 318/320). FIG. 4G illustrates the resulting structure after growthof epitaxial source/drain cap 490, which can be p-type, and compriseprimarily germanium but may contain less than 20 atomic % tin or othersuitable alloying material, as previously explained. As will beappreciated in light of this disclosure, conventional processes andforming techniques can be used to fabricate the FinFET transistorstructure having the bi-layer source/drain structure as describedherein.

As will further be appreciated, note that an alternative to the tri-gateconfiguration as shown is a double-gate architecture, which wouldinclude a dielectric/isolation layer on top of the fin 410. Further notethat the example shapes of the liner 480 and cap 490 making up thesource/drain regions shown in FIG. 4G are not intended to limit theclaimed invention to any particular source/drain types or formationprocesses, and other source/drain shapes will be apparent in light ofthis disclosure (e.g., round, square or rectangular source/drain regionsmay be implemented).

FIG. 5A shows a perspective view of a nanowire transistor structureformed in accordance with one embodiment of the present invention. Ananowire transistor (sometimes referred to as gate-all-around FET) isconfigured similarly to a fin-based transistor, but instead of a fin, ananowire is used and the gate material generally surrounds the channelregion on all sides. Depending on the particular design, some nanowiretransistors have, for instance, four effective gates. FIG. 5Aillustrates a nanowire channel architecture having two nanowires 510,although other embodiments can have any number of wires. The nanowires510 can be implemented, for example, with p-type silicon or germanium orSiGe nanowire. As can be seen, one nanowire 510 is formed or otherwiseprovided in a recess of substrate 400 and the other nanowire 510effectively floats in the source/drain material bi-layer constructioncomprising liner 580 and cap 590. Just as with the fin configuration,note that the nanowire 510 can be replaced in the source/drain regionswith a bi-layer construction of source/drain material as describedherein (e.g., relatively thin silicon or germanium or SiGe liner andrelatively thick high concentration germanium cap). Alternatively, thebi-layer construction can be provided around the originally formednanowire 510 as shown (where liner 580 is provided around nanowire 510,and cap 590 is then provided around liner 580). FIG. 5B also illustratesa nanowire configuration having multiple nanowires 510, but in thisexample case, non-active material 511 is not removed from between theindividual nanowires during the nanowire forming process, which can becarried out using various conventional techniques, as will beappreciated in light of this disclosure. Thus, one nanowire 510 isprovided in a recess of substrate 400 and the other nanowire 510effectively sits on top of the material 511. Note the nanowires 510 areactive through the channel, but the 511 material is not. As can be seen,the bi-layer source/drain construction of liner 580 and cap 590 isprovided around all other exposed surfaces of the nanowires 510.

Example System

FIG. 6 illustrates a computing system 1000 implemented with one or moretransistor structures configured in accordance with an exampleembodiment of the present invention. As can be seen, the computingsystem 1000 houses a motherboard 1002. The motherboard 1002 may includea number of components, including but not limited to a processor 1004and at least one communication chip 1006, each of which can bephysically and electrically coupled to the motherboard 1002, orotherwise integrated therein. As will be appreciated, the motherboard1002 may be, for example, any printed circuit board, whether a mainboard or a daughterboard mounted on a main board or the only board ofsystem 1000, etc. Depending on its applications, computing system 1000may include one or more other components that may or may not bephysically and electrically coupled to the motherboard 1002. These othercomponents may include, but are not limited to, volatile memory (e.g.,DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digitalsignal processor, a crypto processor, a chipset, an antenna, a display,a touchscreen display, a touchscreen controller, a battery, an audiocodec, a video codec, a power amplifier, a global positioning system(GPS) device, a compass, an accelerometer, a gyroscope, a speaker, acamera, and a mass storage device (such as hard disk drive, compact disk(CD), digital versatile disk (DVD), and so forth). Any of the componentsincluded in computing system 1000 may include one or more transistorstructures as described herein (e.g., having a bi-layer source/drainstructure comprising a relatively thin p-type silicon or germanium orSiGe liner and a relatively thicker p-type high germanium content cap).These transistor structures can be used, for instance, to implement anon-board processor cache or memory array. In some embodiments, multiplefunctions can be integrated into one or more chips (e.g., for instance,note that the communication chip 1006 can be part of or otherwiseintegrated into the processor 1004).

The communication chip 1006 enables wireless communications for thetransfer of data to and from the computing system 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing system 1000 may include a plurality ofcommunication chips 1006. For instance, a first communication chip 1006may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 1006 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integratedcircuit die packaged within the processor 1004. In some embodiments ofthe present invention, the integrated circuit die of the processorincludes onboard memory circuitry that is implemented with one or moretransistor structures (e.g., PMOS or CMOS) as described herein. The term“processor” may refer to any device or portion of a device thatprocesses, for instance, electronic data from registers and/or memory totransform that electronic data into other electronic data that may bestored in registers and/or memory.

The communication chip 1006 may also include an integrated circuit diepackaged within the communication chip 1006. In accordance with somesuch example embodiments, the integrated circuit die of thecommunication chip includes one or more circuits implemented with one ormore transistor structures as described herein (e.g., on-chip processoror memory). As will be appreciated in light of this disclosure, notethat multi-standard wireless capability may be integrated directly intothe processor 1004 (e.g., where functionality of any chips 1006 isintegrated into processor 1004, rather than having separatecommunication chips). Further note that processor 1004 may be a chip sethaving such wireless capability. In short, any number of processor 1004and/or communication chips 1006 can be used. Likewise, any one chip orchip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, anetbook, a notebook, a smartphone, a tablet, a personal digitalassistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer,a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the system 1000may be any other electronic device that processes data or employs lowresistance transistor devices as described herein (e.g., PMOS and CMOScircuitry).

Numerous embodiments will be apparent, and features described herein canbe combined in any number of configurations. One example embodiment ofthe present invention provides a transistor device. The device includesa substrate having a channel region, a gate electrode above the channelregion, and source and drain regions formed on or in the substrate andadjacent to the channel region. Each of the source and drain regions hasa total thickness comprising a p-type liner of silicon or germanium orsilicon germanium, and a p-type cap having a germanium concentration inexcess of 80 atomic %, wherein the liner is less than 50% of the totalthickness. In some cases, the device is one of a planar, FinFET, ornanowire PMOS transistor. In some cases, the device further includesmetal-germanide source and drain contacts. In some cases, the thicknessratio of liner thickness to cap thickness is 2:5, or less (liner is 40%or less of the total thickness). In some cases, the thickness ratio ofliner thickness to cap thickness is 1:5, or less (liner is 20% or lessof the total thickness). In some cases, each of the liners has athickness in the range of about one monolayer to 10 nm, and each of thecaps has a thickness in the range of about 50 nm to 500 nm. In somecases, at least one of the liners and/or caps has at least one of agraded concentration of germanium and/or p-type dopant. For instance, insome cases, at least one of the liners has a germanium concentrationthat is graded from a base level concentration compatible with thesubstrate to a high concentration in excess of 50 atomic %. In one suchcase, the high concentration is in excess of 90 atomic %. In some cases,at least one of the liners has a p-type dopant concentration that isgraded from a base level concentration compatible with the substrate toa high concentration in excess of 1E20 cm-3. In one such case, thep-dopant of the one or more liners is boron. In some cases, at least oneof the caps has a germanium concentration in excess of 95 atomic %. Insome cases, at least one of the caps has a germanium concentration thatis graded from a base level concentration compatible with thecorresponding liner to a high concentration in excess of 80 atomic %. Insome cases, at least one of the caps has a p-type dopant concentrationthat is graded from a base level concentration compatible with thecorresponding liner to a high concentration in excess of 1E20 cm-3. Inone such case, the p-dopant of the one or more caps is boron. In somecases, at least one of the caps further comprises tin. Numerousvariations will be apparent. For instance, in some example cases thesubstrate is a silicon-containing substrate. In some such cases, thep-type liner comprises silicon or silicon germanium. In other examplecases, the substrate is a germanium substrate. In some such cases, thep-type liner is p-type germanium. In some example such cases, each lineris included in the composition of the corresponding cap (such that adistinct and separate liner layer may not be discernible from a distinctand separate cap layer). In some cases, at least one of the caps furthercomprises misfit dislocations and/or threading dislocations and/ortwins, while in other cases, the caps are free of misfit dislocations,threading dislocations, and twins. Another embodiment of the presentinvention includes an electronic device that includes a printed circuitboard having an integrated circuit including one or more transistordevices as variously defined in this paragraph. In one such case, theintegrated circuit comprises at least one of a communication chip and/ora processor. In some cases, the electronic device is a computing device.

Another embodiment of the present invention provides an integratedcircuit. The circuit includes a substrate (e.g., silicon, SiGe, orgermanium) having a channel region, a gate electrode above the channelregion, source and drain regions formed on or in the substrate andadjacent to the channel region, and metal-germanide source and draincontacts. Each of the source and drain regions has a total thicknesscomprising a p-type liner of silicon or germanium or silicon germaniumand a p-type cap having a germanium concentration in excess of 80 atomic%, wherein the liner is 40% or less of the total thickness. In somecases, the thickness ratio of liner thickness to cap thickness is 1:5,or less. In some case, at least one of the caps further comprises tin.

Another embodiment of the present invention provides a method forforming a transistor device. The method includes providing a substratehaving a channel region, providing a gate electrode above the channelregion, and providing source and drain regions formed on or in thesubstrate and adjacent to the channel region. Each of the source anddrain regions has a total thickness comprising a p-type liner of siliconor germanium or silicon germanium and a p-type cap having a germaniumconcentration in excess of 80 atomic %, wherein the liner is less than50% of the total thickness. In some cases, the method includes providingmetal-germanide source and drain contacts. In some cases, the thicknessratio of liner thickness to cap thickness is 2:5, or less. In somecases, at least one of the liners and/or caps has at least one of agraded concentration of germanium and/or p-type dopant. In some cases,at least one of the caps further comprises tin (or other suitable straininducer).

The foregoing description of example embodiments of the invention hasbeen presented for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Many modifications and variations are possible in lightof this disclosure. For instance, while some embodiments of the presentinvention utilize in situ boron doping of germanium, other embodimentsmay use an intrinsic germanium that after its deposition is subsequentlysubjected to p-type dopant implantation and annealing processes toprovide the desired p-type doping concentration. Moreover, someembodiments may include source and drain regions fabricated as describedherein, but still use conventional processing (e.g., implantation andannealing) to form the tips of the source and drain regions. In suchembodiments, the tips may have a lower germanium and/or p-type dopantconcentration than the main source/drain region, which may be acceptablein some applications. In still other embodiments, only tips of thesource and drain regions may be configured with the high germanium andp-type dopant concentrations and the main portions of the source anddrain regions may have conventional or otherwise lower germanium/dopantconcentrations. It is intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto.

1. An integrated circuit device, comprising: a semiconductor fincomprising at least one of silicon and germanium; a gate structurearound the semiconductor fin, the gate structure including a gateelectrode and a gate dielectric between the semiconductor fin and thegate electrode; a source structure or drain structure adjacent thesemiconductor fin, the source structure or drain structure including afirst portion and a second portion, the first portion comprising atleast one of silicon and germanium, and the second portion comprising ap-type dopant and germanium, the second portion having a germaniumconcentration in excess of 80 atomic %, wherein the first portion isthinner than the second portion, and wherein the first portion isbetween the second portion and the semiconductor fin; and a contactstructure on the second portion of the source structure or drainstructure.
 2. The device of claim 1, wherein the semiconductor finconsists essentially of silicon, and the first portion of the sourcestructure or drain structure consists essentially of silicon or siliconand germanium.
 3. The device of claim 1, wherein the semiconductor finconsists essentially of germanium, and the first portion of the sourcestructure or drain structure consists essentially of silicon or siliconand germanium.
 4. The device of claim 1, wherein the semiconductor finconsists essentially of silicon and germanium, and the first portion ofthe source structure or drain structure consists essentially of siliconor silicon and germanium.
 5. The device of claim 1, wherein gatestructure is on three sides of the semiconductor fin.
 6. The device ofclaim 1, wherein the second portion further comprises tin, the tinconcentration being in the range of 3 atomic % to 8 atomic %.
 7. Acomputing device, comprising: a board; and a component coupled to theboard, the component including an integrated circuit structure,comprising: a semiconductor fin comprising at least one of silicon andgermanium; a gate structure around the semiconductor fin, the gatestructure including a gate electrode and a gate dielectric between thesemiconductor fin and the gate electrode; a source structure or drainstructure adjacent the semiconductor fin, the source structure or drainstructure including a first portion and a second portion, the firstportion comprising at least one of silicon and germanium, and the secondportion comprising a p-type dopant and germanium, the second portionhaving a germanium concentration in excess of 80 atomic %, wherein thefirst portion is thinner than the second portion, and wherein the firstportion is between the second portion and the semiconductor fin; and acontact structure on the second portion of the source structure or drainstructure.
 8. The computing device of claim 7, further comprising: amemory coupled to the board.
 9. The computing device of claim 7, furthercomprising: a communication chip coupled to the board.
 10. The computingdevice of claim 7, wherein the component is a packaged integratedcircuit die.